Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6762076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Apr 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.