High coupling floating gate transistor
US6762093B2 · kind B2 · utility
11Cited by
18References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2002 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A floating gate transistor includes a first floating gate portion extending horizontally over a channel region. A second floating gate portion vertically extends upwardly from the first floating gate portion to be coupled to a control gate. The second floating gate portion can be formed in a container shape with the control gate formed within the container floating gate. The transistor allows the die real estate occupied by the transistor to be reduced while maintaining the coupling area between the floating and control gates. The transistor can be used in non-volatile memory devices, such as flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.