Paul Rudeck
46Patents
14h-index
9Co-inventors
70Inventor score
Filing activity: Mar 28, 1988 → Jun 15, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6272047A | Flash memory cell | Physics | 56 | Expired |
| US4893163A | Alignment mark system for electron beam/optical mixed lithography | Electricity | 51 | Expired |
| US6849501B2 | Methods for fabricating an improved floating gate memory cell | Electricity | 49 | Expired |
| US7212435B2 | Minimizing adjacent wordline disturb in a memory device | Physics | 38 | Expired |
| US6384447B2 | Flash memory cell for high efficiency programming | Physics | 36 | Expired |
| US6798699B2 | Flash memory device and method of erasing | Physics | 25 | Expired |
| US6449189B2 | Flash memory cell for high efficiency programming | Physics | 24 | Expired |
| US6680508B1 | Vertical floating gate transistor | Electricity | 24 | Expired |
| US6461915B1 | Method and structure for an improved floating gate memory cell | Electricity | 21 | Expired |
| US6445619B1 | Flash memory cell for high efficiency programming | Physics | 20 | Expired |
| US6657250B1 | Vertical flash memory cell with buried source rail | Electricity | 18 | Expired |
| US6563741B2 | Flash memory device and method of erasing | Physics | 16 | Expired |
| US7272039B2 | Minimizing adjacent wordline disturb in a memory device | Physics | 16 | Expired |
| US6297092A | Method and structure for an oxide layer overlaying an oxidation-resistant layer | Electricity | 15 | Expired |
| US6762093B2 | High coupling floating gate transistor | Electricity | 11 | Expired |
| US6713350B2 | Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack | Electricity | 11 | Expired |
| US7257024B2 | Minimizing adjacent wordline disturb in a memory device | Physics | 10 | Expired |
| US6916707B2 | High coupling floating gate transistor | Electricity | 8 | Expired |
| US7148547B2 | Semiconductor contact device | Electricity | 7 | Expired |
| US7420240B2 | Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack | Electricity | 7 | Expired |
| US6881628B2 | Vertical flash memory cell with buried source rail | Electricity | 7 | Expired |
| US7294567B2 | Semiconductor contact device and method | Electricity | 6 | Expired |
| US6774431B2 | High coupling floating gate transistor | Electricity | 5 | Expired |
| US7932557B2 | Semiconductor contact device | Electricity | 5 | Active |
| US7015098B2 | Methods and structure for an improved floating gate memory cell | Electricity | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.