High performance CMOS device structure with mid-gap metal gate

US6762469B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anda C. Mocuta · Hopewell Junction, US
• Meikei Ieong · Wappingers Falls, US
• Ricky S. Amos · Rhinebeck, US
• Diane C. Boyd · Lagrangeville, US
• Dan M. Mocuta · Herent, BE
• Huajie Chen · Danbury, US

Key dates

• Filing date: Apr 19, 2002
• Grant date: Jul 13, 2004
• Expiry date: Apr 19, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0172

Abstract

High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.