Read/write timing calibration of a memory array using a row or a redundant row
US6763444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2001 |
| Grant date | Jul 13, 2004 |
| Priority date | — |
| Expiry date | Apr 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration. Use of a nonutilized row or redundant row for read/write timing calibration according to the present invention enables calibration to be performed during operation of a memory device without compromising data integrity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.