Implantation into high-K dielectric material after gate etch to facilitate removal
US6764898B1 · kind B1 · utility
40Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Jun 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.