Fabrication method for semiconductor integrated circuit device
US6764950B2 · kind B2 · utility
25Cited by
13References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.