Non-volatile memory transistor array implementing “H” shaped source/drain regions and method for fabricating same
US6765259B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Nov 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory (NVM) array including a plurality of 2-bit NVM transistors arranged in a plurality of rows extending along a first axis, and a plurality of columns extending along a second axis, perpendicular to the first axis. The non-volatile memory array includes a plurality of field isolation regions located in a semiconductor substrate and a plurality of word lines extending over the semiconductor substrate along the first axis, wherein the word lines form control gates of the 2-bit NVM transistors. Oxide-nitride-oxide (ONO) structures are formed between the substrate and the word lines, wherein the nitride layer provides floating gate storage for the NVM transistors. A plurality of H-shaped source/drain regions are defined by the field isolation regions and the word lines, wherein each source/drain region serves as a source/drain for four different NVM transistors in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.