Semiconductor structure and method for determining critical dimensions and overlay error
US6765282B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor structure and a method of determining an overlay error produced during formation of the semiconductor structure are disclosed. The semiconductor structure comprises a first two-dimensional periodic pattern and a second two-dimensional periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second two-dimensional periodic patterns indicates the magnitude and direction of an overlay error caused during the formation of the first and second two-dimensional periodic patterns. The semiconductor allows one to independently determine the overlay errors in linearly independent directions by directing a light beam of known optical properties onto the first and second two-dimensional periodic patterns and by analyzing the diffracted beam by comparison with reference data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.