Low frequency testing, leakage control, and burn-in control for high-performance digital circuits
US6765414B2 · kind B2 · utility
8Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318502
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.