Semiconductor memory device with word line shift configuration
US6765832B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2003 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Sep 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In each word line driver, an output node is precharged to a power supply voltage prior to a row select operation and disconnected from the power supply voltage in the row select operation. Further, each first node is connected to a corresponding second node selectively driven to a ground voltage according to a row address through a control switch that is turned on in the row select operation. In each shift switch, output nodes corresponding to word lines other than a defective word line and spare word lines are connected to a second node of a corresponding word line or a word line adjacent thereto through a plurality of transistor switches selectively turned on in accordance with shift control, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.