Refresh control circuitry for refreshing storage data
US6765838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Aug 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh array activating signal is activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the specific address bit(s) is (are) utilized as upper bit(s) of the refresh address. Thus, in the self-refresh mode, refresh can be performed for a prescribed address region at uniform intervals, with a lengthened refresh interval, consuming less current. A semiconductor memory device is provided which allows current consumption to be distributed on a time basis and to be reduce in a self-refresh mode is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.