Processing tester information by trellising in integrated circuit technology development
US6766265B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Jul 20, 2004 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processing tester information is provided. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.