Semiconductor structure and method for determining critical dimensions and overlay error
US6767680B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Oct 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor structure and a method of determining an overlay error produced during formation of a semiconductor structure is disclosed. The semiconductor structure comprises a first periodic pattern and a second periodic pattern, which overlap with each other, wherein a relative position between the overlapping first and second periodic patterns contains information on the magnitude and the sign of an overlay error in a predefined direction that has been caused during the formation of the first and second periodic patterns. The overlay error is determined by directing a light beam of known optical properties onto the first and second periodic patterns and by analyzing the diffracted beam by comparison with reference data. By providing two differently oriented diffracting areas, each comprising first and second periodic patterns, the overlay error in two dimensions can be determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.