Methods of making relaxed silicon-germanium on insulator via layer transfer
US6767802B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a SiGe layer overlying an insulator are provided. A layer of SiGe is deposited on a substrate and implanted with ion to form a defect region within the SiGe material below its surface. The SiGe layer is then patterned and transferred by contact bonding to an insulator on a second substrate. After contact bonding the structure is annealed to split the SiGe layer along the defect region. The splitting anneal will relax the SiGe layer. Additional annealing at higher temperatures may be used to further relax the SiGe layer. A layer of strained silicon may then be epitaxial deposited on the resulting structure of relaxed SiGe on insulator. Another method provides for epitaxially depositing a layer of silicon over the SiGe layer prior to patterning. The silicon layer would then be bonded to the insulator on the second substrate. The splitting anneal and additional anneals, if any, should then induce strain into the silicon layer. The silicon layer would then remain over the insulator after the SiGe layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.