Method for forming patterns for semiconductor devices
US6767828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.