Method of making a shaped gate electrode structure, and device comprising same
US6767835B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Oct 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure. In another illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a first layer of polysilicon above the gate insulation layer, implanting a dopant material into the first layer of polysilicon to form a doped region having a dopant concentration level in the layer of polysilicon, forming a second layer of polysilicon above the doped region of the first layer of polysilicon, th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.