Multichip wafer-level package and method for manufacturing the same
US6768207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip. The bump ring is disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device. The bumps electrically connect the internal bonding pads of the first chip to the bonding pads of the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.