Selection circuit for accurate memory read operations
US6768679B1 · kind B1 · utility
417Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Jul 27, 2004 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.