Patent · US Expired

Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module

US6770530B2 · kind B2 · utility

4Cited by

3References

10Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dirk Efferenn · Dresden, DE
Hans-Peter Moll · Dresden, DE
Andreas Wich-Glasen · Neustadt an der Donau, DE

Key dates

Filing date	Mar 10, 2003
Grant date	Aug 3, 2004
Priority date	—
Expiry date	Mar 10, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.