Operating techniques for reducing program and read disturbs of a non-volatile memory
US6771536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Aug 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.