Low power auto-refresh circuit and method for dynamic random access memories
US6771553B2 · kind B2 · utility
17Cited by
29References
110Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Aug 3, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.