Process scheme for improving electroplating performance in integrated circuit manufacture
US6774039B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Copper bus bars are formed between adjacent die on a wafer during the process flow. The bus bars are between 50 and 100 &mgr;m wide and between 2 and 5 &mgr;m deep. A barrier layer is formed between the bus bars and the die to prevent copper diffusion. A dielectric layer is deposited over the bus bars and die and etched with contacts and features, such as vias. A seed layer is subsequently deposited over the wafer, which allows electrical conductance between the bus bars and the die during a subsequent electroplating process to fill the features and contacts. The bus bars carry electroplating current from the die edge to the die center. As a result, current does not need to be carried by a low sheet resistivity seed layer from the wafer edge to the center. This allows the seed layer to be thinner and of materials other than copper. Further, thinner seed layers allow thicker barrier layer for more reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.