Digital dual-loop DLL design using coarse and fine loops
US6774690B2 · kind B2 · utility
41Cited by
12References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.