Semiconductor memory device switchable to twin memory cell configuration
US6775177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | Aug 10, 2004 |
| Priority date | — |
| Expiry date | Nov 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row address decoder of a semiconductor memory device generates internal row address signals RAD<0:11> and /RAD<0:11> by switching most significant bit and least significant bit of row address signals RA<0:11> and /RA<0:11> that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD<0> and /RAD<0> of the internal row address signals corresponding to the most significant bits RA<11> and /RA<11> of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.