Random access memory
US6777732B1 · kind B1 · utility
1Cited by
17References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.