Delay lock loop having an edge detector and fixed delay
US6777990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Mar 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.