Phase detector for all-digital phase locked and delay locked loops
US6779126B1 · kind B1 · utility
37Cited by
20References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Nov 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop. Methods of operation are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.