Patent · US Expired

Method for controlling the quality of a lithographic structuring step

US6780552B2 · kind B2 · utility

3Cited by

5References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thorsten Schedel · Dresden, DE
Jens Zimmermann · Dresden, DE
Sebastian Schmidt · Weisendorf, DE

Key dates

Filing date	Jun 19, 2002
Grant date	Aug 24, 2004
Priority date	—
Expiry date	Sep 30, 2022

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/20
WIPO fieldOptics
WIPO sectorInstruments

Abstract

After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.