BiCMOS integration scheme with raised extrinsic base
US6780695B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2003 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.