METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY

US6780708B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Hiroyuki Kinoshita · San Jose, US
• Yu Sun · Saratoga, US
• Basab Banerjee · Ballston Lake, US
• Christopher Foster · Austin, US
• John R. Behnke · Austin, US
• Cyrus E. Tabery · Sunnyvale, US

Key dates

• Filing date: Mar 5, 2003
• Grant date: Aug 24, 2004
• Expiry date: Apr 22, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.