Method for eliminating voiding in plated solder
US6780751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Oct 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for plating solder is provided. In accordance with the method, a die having a seed metallization thereon is provided. The seed metallization is microetched (85) with a solution comprising an acid and an oxidizer, thereby forming an etched seed metallization. An under bump metallization (UBM) is then electroplated (87) onto the etched seed metallization, and a lead-free solder composition, such as SnCu, is electroplated (91) onto the UBM. A method for reflowing solder is also provided, which may be used in conjunction with the method for plating solder. In accordance with this later method, the substrate is subjected to a seed metallization etch (137), followed by a microetch (141). A solder flux is then dispensed onto the substrate (147) and the solder is reflowed (149).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.