Etch back of interconnect dielectrics
US6780756B1 · kind B1 · utility
15Cited by
8References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric regions 20. Another embodiment of the invention is a method of fabricating a semiconductor wafer 4 where the height of the interconnects 17 is greater than the height of the dielectric regions 20.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.