Layout of a folded bitline DRAM with a borderless bitline

US6781181B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Kuen-Chy Heo · Chiayi, TW
• Jeng-Ping Lin · Taoyuan, TW

Key dates

• Filing date: Jun 4, 2003
• Grant date: Aug 24, 2004
• Expiry date: Jun 4, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is disposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folded bitline DRAM, and a folded bitline DRAM with bordless bitline contact window.