Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
US6781877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Sep 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.