MRAM semiconductor memory configuration with redundant cell arrays
US6781896B2 · kind B2 · utility
5Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.