Memory cell sensing integrator
US6781906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Nov 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.