System for reducing test data volume in the testing of logic products
US6782501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Oct 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.