Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices

US6784091B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• Infineon Technologies AG · DE

Inventors

• Joachim Nuetzel · Fishkill, US
• Christian Arndt · Birkenfeld, DE
• Greg Costrini · Hopewell Junction, US
• Michael C. Gaidis · Yorktown Heights, US
• Xian Jay Ning · Shanghai, CN

Key dates

• Filing date: Jun 5, 2003
• Grant date: Aug 31, 2004
• Expiry date: Jun 5, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B61/22
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.