Fully depleted SOI transistor with elevated source and drain
US6787424B1 · kind B1 · utility
141Cited by
93References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2001 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Feb 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6741
Abstract
A method of manufacturing an integrated circuit utilizes a thin film substrate. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.