Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
US6787431B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by a metal frame is formed on the semiconductor wafer. Subsequently, the alignment mark region and the metal frame are completely buried in at least one dielectric layer, in order to define an alignment mark area in the alignment mark region on the dielectric layer with a photolithography process. The boundary of the alignment mark area lies at a uniform distance within the boundary of the alignment mark region, defined by the metal frame. Subsequently (to uncover the alignment mark area by an anisotropic etching of the dielectric layer), the etching depth is defined in such a way that the alignment mark opening extends at least as far as the level of the metal frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.