Double pattern and etch of poly with hard mask
US6787469B2 · kind B2 · utility
71Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.