Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region
US6787906B1 · kind B1 · utility
23Cited by
16References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Feb 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.