Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
US6787911B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1999 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | May 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A look material is then deposited to fill the gaps bet n metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A prove layer is deposited on top of the metal lines and the look material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photoresist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.