Substrate structure of flip chip package
US6787918B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jun 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.