Semiconductor buffer circuit with a transition delay circuit
US6788126B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transition delay circuit having an input terminal and an output terminal is disclosed. According to one embodiment, the transition delay circuit also includes a first MOS capacitor, a second MOS capacitor, and a delay circuit. The first MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor has a different polarity than the first MOS capacitor. The delay circuit includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.