Memory device and operation thereof
US6788602B2 · kind B2 · utility
2Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.