Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
US6788613B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.