Interstream control and communications for multi-streaming digital processors
US6789100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.