Determining a possible cause of a fault in a semiconductor fabrication process
US6790680B1 · kind B1 · utility
6Cited by
0References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Nov 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67276
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining a possible cause of a fault in a semiconductor fabrication process. The method includes determining a first fault in a first processing tool executing under first operating conditions and determining a second fault in a second processing tool executing under second operating conditions. The method further includes identifying a possible source of the second fault based on at least the first operating conditions of the first processing tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.